Auto-centered phase-locked loop

ABSTRACT

A multi-band processing system for automatically tuning the oscillator of a phase-locked loop to the frequency and phase of an applied input. The system includes an error detection circuit, a frequency controller, a scaling circuit, and a phase and frequency controller. The applied input and the oscillator output are coupled to the error detection circuit whose error output drives a charge pump/filter circuit. An error signal is derived from the difference between the loop charge pump output V 1  and a preset charge pump zero error reference signal V ref , wherein the frequency controller regulates the oscillator output frequency according to a frequency error component of V 1  -V ref , the scaling circuit scales the oscillator output frequency according to a system scaling signal N, and the phase and frequency controller adjusts the oscillator output frequency and phase according to V 1  -V ref , when a 1/N multiple of the frequency of the oscillator output is compared in the error detection circuit to the frequency of the applied input.

BACKGROUND OF THE INVENTION

The present invention relates to a phase-locked loop in the frequencyacquisition section of a computer system.

In writing data on a magnetic recording disk, spin rate and writingfrequency, in part, determine the number (density) of cells (positionsfor recording information) which can be defined on a given track. Eachcell represents a set of magnetic dipoles which can be magneticallyoriented by a magnetic field from a recording head. Data is stored andretrieved based upon changes (or transitions) in dipole orientation fromcell to cell to cell.

Generally, system storing and retrieving frequency (i.e.,writing/reading frequency) is set to maximize cell density. In a systemwith a single frequency, the maximum cell density is limited by thecapacity of the shortest (innermost) track on the disk. As a result, thelonger outer tracks are under-utilized.

In a known industry approach to increasing disk cell density, each diskis segmented into concentric bands, each band containing a plurality oftracks. Each successive band from the center out is accorded a higherwriting/reading frequency than the next prior band. This approachenables the defining of a greater number of cells in each successiveband of longer tracks, and thus increases total disk cell density.

The head data signal generated when retrieving data from a medium isconverted from analog to digital format and is then applied to a dataseparator circuit. A phase-locked loop circuit is conventionally used toextract a timing signal from the digital read signal. This timing signalis applied to the data separator to enable extraction of data from thedigital read signal.

The timing signal output of the phase-locked loop is typically suppliedby a voltage or current controlled oscillator, which is driven basedupon frequency and phase differences between the oscillator output andthe loop input. These differences are detected by an error detectorcircuit (e.g., a frequency/phase comparator) and cause a charge pumpcircuit to issue a control signal to a control input of the oscillatorto effect frequency/phase adjustments to the oscillator output.

In operation of a multi-band system, the oscillator can be drivenapproximately to the band frequency of the data input signal it nextexpects to acquire by applying an appropriate control signal to theoscillator during the head in-transit period. Hence, hardwarerequirements are relaxed in view of the smaller frequency swing (if any)which later will be required to tune the oscillator to the actualfrequency of the data input signal when it is received. This minimizesthe voltage swing demanded of the charge pumps used to drive theoscillator. Consequently, if the oscillator is about at the frequency ofthe next expected data input frequency, then when the next expected datainput signal is applied to the loop, the loop will be able to drive theoscillator quickly to the frequency/phase of that input.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for efficientlyacquiring any one of a set of band frequencies in a multi-band operatingsystem. In general, the invention provides an arrangement for detectingfrequency-related error in the output of an oscillator of a phase-lockedloop, and based upon that error, driving the oscillator to reduce thaterror This arrangement is also responsive to significant jumps in theloop input frequency, such that occurs when bands are switched, whichare accommodated by causing similar significant jumps in the oscillatorfrequency.

In one aspect of the present invention, a phaselocked loop includes anoscillator, a multi-input error detector circuit, and an oscillatordrive circuit. The loop is switchable between various ones of aplurality of preset operating frequencies. Each one of the presetfrequencies is represented with a respective scaling value and thepresent scaling value is represented as N. A 1/N multiplier circuit iscoupled between the oscillator output and a first input of the errordetector circuit, with the scaling value N being applied to the 1/Nmultiplier circuit, and with a 1/N multiple of the oscillator outputfrequency being supplied by the 1/N multiplier circuit to the errordetector circuit as (1/N)F_(vco). The error detector circuit has asecond input for receiving a system input signal having a frequencyF_(in), with (1/N)F_(vco) being compared in the error detector circuitto F_(in). The error detector circuit generates an output V₁representative of phase and/or frequency error between F_(in) and(1/N)F_(vco), where V₁ is equal to a fixed value V_(ref) when there isno phase or frequency error between F_(in) and (1/N)F_(vco). Theoscillator drive circuit includes an oscillator drive signal sourcecircuit coupled to and for supplying a drive signal to an input of theoscillator, and a low pass filter/driver circuit for receiving V₁ andV_(ref) and for detecting a low frequency error component, V_(low), ofV₁ When V₁ does not equal V_(ref). V_(low) represents the low frequencycomponent error of the error between F_(in) and (1/N)F_(vco). The lowpass filter/driver circuit outputs a control signal V₂ to an input ofthe oscillator drive signal source circuit for continuously adjustingthe drive signal. This adjustment follows control signal Vz and servesfor driving the oscillator until (1/N)F_(vco) is at F_(in) and V_(low)is at zero.

Various embodiments of the invention may include any of the followingfeatures.

A band range select circuit, coupled to the low pass filter/drivercircuit, may provide for scaling the control signal V₂ according to thescaling value N. The band range select circuit may include a binarygated switch. A phase and frequency control circuit may be providedwhich is responsive to the difference between V₁ and V_(ref). This phaseand frequency control circuit may be coupled between the output of thelow pass filter/driver circuit and the oscillator input and serves toadjust the drive signal output of the oscillator drive signal sourcecircuit before the drive signal is applied to the input of theoscillator. The thus adjusted drive signal thereby causes (1/N)F_(vco)to be driven toward F_(in) in magnitude and in phase. The phase andfrequency control circuit may be a linearized multiplier circuit.

The filter/driver circuit may include an integrator circuit. Theoscillator drive signal source circuit may include a voltage controlledcurrent source circuit, wherein V₁ and V_(ref) are applied to theintegrator and the integrator output is applied to the oscillator drivesignal source circuit. The integrator may include a resistive input forreceipt of V₁ and a second input for receipt of V_(ref), the integratoroutput being coupled to the integrator's resistive input via acapacitor, Wherein (1/N)F_(vco) is held at F_(in) by the charge on thecapacitor when V₁ is equal to V_(ref). The oscillator drive circuit mayinclude a range multiplier circuit having a first input for receipt ofthe integrator output and a second input for receipt of the band rangeselect output, wherein the integrator output is multiplied by the valueof the band range select circuit output to generate control signal V₂.The oscillator drive circuit may also include a pair of voltage levelshifting current mirrors wherein the output of the range multipliercircuit is coupled to the oscillator drive signal source via the currentmirrors.

The multi-input error detector circuit may include a frequencycomparator circuit, a phase and frequency comparator circuit, amultiplexer circuit and a charge pump/filter circuit, wherein therespective outputs of the comparators are selectively coupled to thecharge pump/filter circuit via the multiplexer circuit. The multiplexercircuit may apply the output of the frequency comparator to the chargepump/filter circuit when the loop is switched from one to another of theplurality of preset frequencies. The oscillator may be a currentcontrolled oscillator.

In another aspect of the present invention, a computer system having amagnetic recording disk having a phase-locked loop includes a currentcontrolled oscillator, the loop being capable of acquiring one of aplurality of preset operating frequencies for use in a system (a) whichrepresents each of the preset frequencies with a respective value of ascaling factor, the current value of the scaling factor being designatedas N, and (b) which supplies a preset reference clock signal at a fixedfrequency F_(in) to the loop, the oscillator circuit having an outputcapable of being driven to a frequency F_(vco) which is N times thefrequency of F_(in).

The system includes an error detector circuit for detecting the phasedifference Δ_(phase) and frequency difference Δ_(freq) between(1/N)F_(vco) and F_(in) and for generating a control signal V₁ basedupon Δ_(phase) and Δ_(freq), wherein control signal V₁ obtains a valueV_(ref) when Δ_(phase) and Δ_(freq) are at a zero level, Wherein V₁-V_(ref) is representative of Δ_(phase) and Δ_(freq), and wherein a lowfrequency signal component V_(low) of V₁ -V_(ref) is representative ofΔ_(freq).

The system further includes a drive signal source circuit for supplyingan oscillator drive signal and a frequency control circuit having aninput coupled to an output of the error detector circuit. The frequencycontrol circuit generates a control signal output based upon the signalcomponent V_(low) and is coupled to an input of the drive signal sourcecircuit, wherein the oscillator drive signal is regulated according tothe value of the control signal output. The system further including ascaling circuit which scales the frequency control circuit outputaccording to the value N, and a linearized multiplier circuit formodulating the scaled oscillator drive signal. The modulated output isapplied as an input to the oscillator. The linearized multiplier circuitis responsive to the value of V₁ -V_(ref), whereby the scaled andmodulated input to the oscillator serves to adjust the oscillator outputF_(vco) to obtain the phase and N times the frequency of F_(in).

In another aspect of the present invention, a method for controlling thefrequency and phase of an oscillator output in a phase-locked loop for amulti-band operating system, wherein each band has its own bandfrequency and is represented by a respective value of a scaling factor,the present value of the scaling factor being designated as N. The loopincludes an oscillator circuit for locking onto the frequency of asystem input signal, an error detector circuit for receiving the systeminput signal, a charge pump circuit coupled to the output of the errordetector circuit, and an oscillator drive circuit whose input is coupledto the output of the charge pump circuit and whose oscillator drivesignal output is coupled to the oscillator input for driving theoscillator output, the oscillator output being coupled to one input ofthe error detector circuit and the system signal input being applied toanother input of the error detector circuit. The error detector circuitissues an error output representative of differences in phase Δ_(phase)and/or frequency Δ_(freq) between the oscillator output frequency or a1/N multiple thereof and the system input signal frequency. The chargepump circuit issues an error signal based upon errors detected by theerror detector circuit, the phase and/or frequency of the oscillatoroutput being adjusted by the oscillator drive circuit according to theerror signal. The method includes the steps of submitting the errorsignal to a filter circuit to extract a low frequency component V_(low)expressive of Δ_(freq), continuously regulating the oscillator drivesignal according to the non-zero value of V_(low), and scaling theoscillator drive signal according to the value of N. Preferably the stepof scaling the oscillator drive signal according to the value of Nincludes driving the oscillator to minimize Δ_(freq). This method mayfurther include the step of modulating the oscillator drive signalaccording to changes in the error control signal in order to minimizeΔ_(phase).

Other advantages and features will become apparent from the followingdescription of the preferred embodiment and from the claims.

BRIEF DESCRIPTION OF THE DRAWING

The drawings are first briefly described below.

FIG. 1 is a block diagram of a simplified embodiment of the invention.

FIG. 2 is a block/schematic diagram of a preferred embodiment of theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An illustrative embodiment of the present invention is shown in thesimplified block diagram of FIG. 1. Phase-locked loop 10 includes errordetector 12, charge pump 14, oscillator driver circuit 15 and oscillator20 (hereinafter VCO). VCO 20 is preferably a current controlledoscillator.

The VCO is maintained at a given frequency F_(vco) according to acontrol current I_(vco) supplied to the oscillator by oscillator drivercircuit 15. The oscillator driver circuit 15 includes a frequencycontroller circuit 16, a control current source 26 and a phase andfrequency control circuit 24. The output I_(vco) of controller 24 isapplied to VCO input 21 to drive the VCO output frequency accordingly.

In this embodiment, the frequency F_(vco) of the VCO 20 is maintained atan N multiple of the frequency F_(in) of a system reference clock input.This system reference clock input is derived relative to or from therate of disk rotation and is related to the frequency F_(data) at whichdata is read from the disk.

The system reference clock input F_(in) and a 1/N multiple (viamultiplier 34) of the oscillator output F_(vco), i.e., (1/N)F_(vco),respectively, are applied to a first and second input of error detector12. Any phase difference (Δphase) or frequency difference (Δfrequency)detected between these input signals by error detector 12 results in anerror output signal output V_(o) which is nonzero. The system data inputF_(data), the frequency at which data is actually read from the disk,and the oscillator output F_(vco) are applied to a third and fourthinput of error detector 12. Any phase difference (Δphase) or frequencydifference (Δfrequency) between these input signals also results in anerror output signal V_(o) which is non-zero.

This error output signal V_(o) is applied through a multiplexer 25 tocharge pump circuit 14 which generates an error voltage V₁ based uponerror signal V_(o). V₁ is an analog signal whose average value isrelated to the frequency error and whose instantaneous value representsboth phase and frequency error. The multiplexer 25 is used to selectwhether the error signal V_(o) is derived from the system referenceclock input F_(in) or the system data input F_(data).

This error voltage V₁ is applied to oscillator driver circuit 15 throughan input 16a of frequency controller 16 and an input 23 ofphase/frequency controller 24. In addition, a system reference voltageV_(ref) is applied on a second input 16b of frequency controller 16.V_(ref) is equal to the d.c. steady-state value of V₁ obtained whenV_(o) indicates no error in detector 12, i.e., V₁ is equal to V_(ref)when (I/N)F_(vco) is equal to F_(in). Hence, the function of frequencycontroller 16 and phase/frequency controller 24 is to drive V₁ to andmaintain V₁ at V_(ref). Accordingly, and generally speaking, the outputI_(vco) of phase frequency controller 24 represents instantaneous phaseand frequency error between (1/N)F_(vco) and F_(in), and the outputvoltage V₂ of frequency controller circuit 16 represents the averagefrequency error between (1/N)F_(vco) and F_(in).

Preferably, frequency controller 16 is an integrator. The integratoracts as a low-pass filter to error signal V₁. Thus, while the integratoris insensitive to transient variances of V₁ (i.e., phase error), it isvery responsive to the low frequency, low, or steady state changes of V₁(i.e., non-trivial frequency error, such as at band change). Theintegrator circuit has very high low-frequency gain compared to thephase/frequency controller 24, and therefore dominates the driving ofthe oscillator to a new frequency following the switching of a band.

Frequency controller 16 also includes a scaling circuit which abruptlyscales the output V₂ of frequency controller 16 whenever the value ofband range select signal N, applied to frequency controller 16 at input16c, is changed (i.e., at band change). The frequency of the VCO outputis thus scaled according to the band range select signal N supplied byband select logic network 30. Band select signal N is derived fromsystem logic otherwise employed in the system to control the location ofthe read/write head over the data disk via head servo unit 32.

In operation, when data is to be read at a new band location on the datadisk, a new data frequency must be acquired by the loop. This frequencyis supplied to a data separator 39 to enable extraction of data from theread data signal. Generally speaking, upon selection of a new bandfrequency, F_(in) is compared by error detector 12 to the appropriatefraction of F_(vco) (via 1/N multiplier 34) according to the new valueof N; the error output signal V_(o) representative of this difference isapplied to charge pump 14 to generate error voltage V₁. V₁ is applied tothe phase/frequency controller 24 which varies I_(vco) to begin thefrequency adjustment of F_(vco). V₁ is also applied to the frequencycontroller 16; and the average or low frequency difference between V₁and V_(ref), represented by the output V₂ of frequency controller 16 isscaled abruptly at band change according to the change in the appliedcontrol signal N. The output of the frequency controller 16, V₂, in turnis applied to control current source 26. The output of the controlcurrent source 26 is used to adjust the output I_(vco) ofphase/frequency controller 24. The adjusted I_(vco) is thereforemodulated by phase/frequency controller 24, and controls the frequencyof the VCO. When (1/N)F_(vco) is at F_(in), then the steady state valueof V₁ will be at V_(ref), and the output V₂ of frequency controller 16Will remain at the most recent level to which it has been driven.Likewise I_(vco) will remain at its level except for instantaneous erroradjustments (such as for phase differences) made by phase/frequencycontroller 24 as a result of the transient components of V₁. Therefore,when V₁ is at V_(ref), the frequency of the VCO will be at N times thefrequency of F_(in), and the two frequencies will be in phase.

The VCO is now approximately set at the frequency of the read data nowintended to be read and decoded. This presetting enables the loop toacquire the actual data frequency with great speed, as is necessary inhigh speed processing systems, without overburdening the charge pumps 14because the charge pumps are essentially relieved of much of the burdenof driving the VCO 20 to a new band frequency.

Turning now to the preferred embodiment of FIG. 2, the function of errordetector 12 is served by phase/frequency comparator 11 and phasecomparator 13. F_(vco) is applied to a first input of phase comparator13 and (1/N)F_(vco) is applied to a first input of phase/frequencycomparator 11 from 1/N multiplier 34. The system reference clock inputF_(in) is applied to a second input of phase/frequency comparator 11 andthe system data input F_(data), the actual frequency at which data willbe read from the disk, is applied to a second input of phase comparator13.

The output signals from both comparators 11, 13 are multiplexed bymultiplexer 25. As stated previous)y, the multiplexer 25 selects whetherthe error signal V_(o) is to be generated by F_(in) or F_(data). Themultiplexer output V_(o), which is representative of the error detectedby the selected one of comparators 11, 13, is applied to a combinationcharge pump/filter circuit 14. The output V₁ of the charge pump filtercircuit 14 is the input to the oscillator driver circuit 15 through thefrequency controller circuit 16. Preferably, frequency controllercircuit 16 (now demarcated in dotted outline) includes an integratorcircuit 17. V_(ref) is applied to the non-inverting input of integrator17 and V₁ is resistively coupled to the integrator's inverting input.Capacitor C1 is coupled between the integrator's output and invertinginput and charges to the level required to drive F_(vco) to NF_(in).Thus, when F_(vco) is at NF_(in), V₁ ideally will be at V_(ref) and thecharge on capacitor Cl will remain at the present value and so maintainthe VCO at its output frequency equal to NF_(in).

The output signal V₂ of frequency controller circuit 16 is derived fromthe output V_(int) of the integrator 17. V₂ is generated by applyingV_(int) through a linearized multiplier 36, to a current mirror 38 and acurrent mirror 40. The mirrors 38, 40 are for level shifting and areconventional. Linearized multiplier 36 multiplies the output V_(int) ofthe integrator according to a range select current I_(RS) established bya band range select circuit 18 based on the present value of N. Bandrange select circuit 18 is a conventional D/A converter, with n gatedswitches each controlled by the binary state of a different one of thebits in the n-bit value of N. Hence, the value of N determines the valueof I_(RS) by switching the fixed current sources R1-R4 so as to directcurrent from the individual source through the mirrors 38, 40. The V₂output is used to drive control current source 26. The output of controlcurrent source 26 is then used to drive the frequency of the VCO 20 viathe output I_(vco) of phase and frequency controller circuit 24.Preferably controller circuit 24 is a linearized multiplier circuit,where I_(vco) is multiplied by the error in V₁ (i.e., V₁ -V_(ref)). Thefrequency of the VCO Output is thus scaled by band range select circuit18 according to band select signal N from band select logic network 30.

The output V₂ optionally may be supplied for use by other timingcircuits 42 such as delay lines, as required by an individualapplication. The input to these circuits are thus scaled as may beuseful or required in a data separation environment.

As a benefit of the present invention, the charge pumps 14 are able tooperate near their optimum level, which is centered about V_(ref). WhenN is switched, the band range select circuit 18 immediately scales V₂ tocause the VCO frequency to jump close to the desired new value. Thecharge pump output V₁ is driven away from V_(ref), and this errorimmediately modulates I_(vco) via the phase/frequency controller 24 toquickly obtain the desired phase and frequency. The low speed adjustmentvia the integrator 17 and the multiplier 36 then adjusts I_(vco) causingV₁ to recover to the optimum value V_(ref) with the VCO 20 operating atthe correct frequency of an N multiple of F_(in).

With the VCO 20 oscillating at an N multiple of F_(in) (i.e. the VCO isat the frequency of the next expected system data input), multiplexer 25switches the loop input from the fixed frequency clock input F_(in) tothe real time system data input F_(data) as applied to comparator 13thereby by-passing 1/N multiplier circuit 34. The loop now detectsfrequency and phase errors and the charge pumps adjust the VCO withlittle effort via phase/frequency controller 24, while the VCO is heldat the new band frequency range by the interaction of integrator 17 andrange select circuit 18. The VCO output is now maintained at thefrequency of and in phase with the data input, thus enabling dataseparator circuit 39 once again to extract the digital data from thesystem input F_(data).

Other embodiments are within the following claims.

What is claimed is:
 1. A system having a phase-locked loop, the loopcomprisingan oscillator, a multi-input error detector circuit and anoscillator drive circuit, the loop being switchable between various onesof a plurality of preset operating frequencies wherein each one of thepreset frequencies is represented with a respective scaling value andwherein a current scaling value is represented as N, a 1/N multipliercircuit coupled to the oscillator output, the scaling value N beingapplied to the 1/N multiplier circuit, a 1/N multiple of the oscillatoroutput frequency being supplied by the 1/N multiplier circuit to theerror detector circuit as (1/N)F_(vco), the error detector circuithaving a second input for receiving an applied input signal,(1/N)F_(vco) being compared in the error detector circuit to thefrequency F_(in) of the applied input signal, the error detector circuitgenerating an output V₁ representative of phase and frequency errorbetween F_(in) and (1/N)F_(vco), where V₁ is equal to a fixed valueV_(ref) when there is no phase or frequency error between F_(in) and(1/N)F_(vco), and the oscillator drive circuit includingan oscillatordrive signal source circuit coupled to and for supplying a drive signalto an input of the oscillator, a low pass filter/driver circuit forreceiving V₁ and V_(ref) and for detecting a low frequency errorcomponent V_(low) of V₁ when V₁ does not equal V_(ref), V_(low)representing the error in frequency between F_(in) and (1/N)F_(vco), thelow pass filter/driver circuit generating a control signal V₂ thatrepresents V_(low), said oscillator drive signal source circuitincluding circuitry for combining V₁ and V₂ to generate said drivesignal thereby to adjust the oscillator until (1/N)F_(vco) isessentially at F_(in) and at least V_(low) is essentially at zero. 2.The system of claim 1 further comprising a band range select circuitcoupled to the low pass filter/driver circuit for scaling the controlsignal V₂ according to the scaling value N.
 3. The system of claim 2wherein the band range select circuit comprises a binary gated switchcircuit.
 4. The system of claim 1 further comprising a phase andfrequency control circuit responsive to the difference between V₁ andV_(ref) and coupled between the output of the low pass filter/drivercircuit and the oscillator input, the phase and frequency controlcircuit adjusting the drive signal output of the oscillator drive signalsource circuit before the drive signal is inputted to the oscillator,the thus adjusted drive signal causing F_(in) to be driven to be equalto and in phase with 1/NF_(vco).
 5. The system of claim 2 wherein theoscillator drive circuit includes a range multiplier circuit having aninput for receipt of the band range select output, wherein the low passfilter/driver circuit output is multiplied by the value of the bandrange select circuit output to generate control signal V₂.
 6. The systemof claim 1 wherein the filter/driver circuit includes an integratorcircuit.
 7. The system of claim 6 further comprising a band range selectcircuit coupled to the low pass filter/driver circuit for scaling thecontrol signal V₂ according to the scaling value N.
 8. A system having aphase-locked loop, the loop comprisingan oscillator, a multi-input errordetector circuit and an oscillator drive circuit, the loop beingswitchable between various ones of a plurality of preset operatingfrequencies wherein each one of the preset frequencies is representedwith a respective scaling value and wherein a current scaling value isrepresented as N, a 1/N multiplier circuit coupled to the oscillatoroutput, the scaling value N being applied to the 1/N multiplier circuit,a 1/N multiple of the oscillator output frequency being supplied by the1/N multiplier circuit to the error detector circuit as (1/N)F_(vco),the error detector circuit having a second input for receiving anapplied input signal, (1/N)F_(vco) being compared in the error detectorcircuit to the frequency F_(in) of the applied input signal, the errordetector circuit generating an output V₁ representative of phase and/orfrequency error between F_(in) and (1/N)F_(vco), where V₁ is equal to afixed value V_(ref) when there is no phase or frequency error betweenF_(in) and (1/N)F_(vco), and the oscillator drive circuit includinganoscillator drive signal source circuit coupled to and for supplying adrive signal to an input of the oscillator, a low pass filter/drivercircuit for receiving V₁ and V_(ref) and for detecting a low frequencyerror component V_(low) of V₁ when V₁ does not equal V_(ref), V_(low)representing the error in frequency between F_(in) and (1/N)F_(vco), thelow pass filter/driver circuit generating a control signal V₂ to aninput of the oscillator drive signal source circuit for continuouslyadjusting the drive signal according to control signal V₂ for drivingthe oscillator until (1/N)F_(vco) is essentially at F_(in) and V_(low)is essentially at zero, and a linearized multiplier circuit responsiveto the difference between V₁ and V_(ref) and coupled between the outputof the oscillator drive signal source circuit and the oscillator input,the linearized multiplier circuit adjusting the drive signal output ofthe oscillator drive signal source circuit before the drive signal isinputted to the oscillator, the thus adjusted drive signal causingF_(in) to be driven to be equal to and in phase with (1/N)F_(vco).
 9. Asystem having a phase-locked loop, the loop comprisingan oscillator, amulti-input error detector circuit and an oscillator drive circuit, theloop being switchable between various ones of a plurality of presetoperating frequencies wherein each of the preset frequencies isrepresented with a respective scaling value and wherein a currentscaling value is represented as N, a 1/N multiplier circuit coupled tothe oscillator output, the scaling value N being applied to the 1/Nmultiplier circuit, a 1/N multiple of the oscillator output frequencybeing supplied by the 1/N multiplier circuit to the error detectorcircuit as (1/N)F_(vco), the error detector circuit having a secondinput for receiving an applied input signal, (1/N)F_(vco) being comparedin the error detector circuit to the frequency F_(in) of the appliedinput signal, the error detector circuit generating an output V₁representative of phase and/or frequency error between F_(in) and(1/N)F_(vco), where V₁ is equal to a fixed value V_(ref) when there isno phase or frequency error between F_(in) and (1/N)F_(vco), theoscillator drive circuit includingan oscillator drive signal sourcecircuit coupled to and for supplying a drive signal to an input of theoscillator, and a low pass filter/driver circuit for receiving V₁ andV_(ref) and for detecting a low frequency error component V_(low) of V₁when V₁ does not equal V_(ref), V_(low) representing the error infrequency between F_(in) and (1/N)F_(vco), the low pass filter/drivecircuit generating a control signal V₂ to an input of the oscillatordrive signal source circuit for continuously adjusting the drive signalaccording to control signal V₂ for driving the oscillator until(1/N)F_(vco) is essentially at F_(in) and V_(low) is essentially atzero, wherein the oscillator drive signal source circuit comprises avoltage controlled current source circuit, the low pass filter/drivercircuit includes an integrator circuit, and V₁ and V_(ref) are appliedto the integrator and the integrator output is applied to the oscillatordrive signal source circuit.
 10. The system of claim 9 wherein theintegrator includes a resistive input for receipt of V₁ and a secondinput for receipt of V_(ref), the integrator output being coupled to theintegrator's resistive input via a capacitor, wherein 1/NF_(vco) is heldat F_(in) by the charge on the capacitor when V₁ is equal to V_(ref).11. A system having a phase-locked loop, the loop comprisinganoscillator, a multi-input error detector circuit and an oscillator drivecircuit, the loop being switchable between various ones of a pluralityof preset operating frequencies wherein each one of the presetfrequencies is represented with a respective scaling value and wherein acurrent scaling value is represented as N, a 1/N multiplier circuitcoupled to the oscillator output, the scaling value N being applied tothe 1/N multiplier circuit, a 1/N multiple of the oscillator outputfrequency being supplied by the 1/N multiplier circuit to the errordetector circuit as (1/N)F_(vco), the error detector circuit having asecond input for receiving an applied input signal, (1/N)F_(vco) beingcompared in the error detector circuit to the frequency F_(in) of theapplied input signal, the errors detector circuit generating an outputV₁ representative of phase and/or frequency error between F_(in) and(1/N)F_(vco), where V₁ is equal to a fixed value V_(ref) when there isno phase or frequency error between F_(in) and (1/N)F_(vco), theoscillator drive circuit includingan oscillator drive signal sourcecircuit coupled to and for supplying a drive signal to an input of theoscillator, and a low pass filter/driver circuit for receiving V₁ andV_(ref) and for detecting a low frequency error component V_(low) of V₁when V₁ does not equal V_(ref), V_(low) representing the error infrequency between F_(in) and (1/N)F_(vco), the low pass filter/drivecircuit generating a control signal V₂ to an input of the oscillatordrive signal source circuit for continuously adjusting the drive signalaccording to control signal V₂ for driving the oscillator until(1/N)F_(vco) is essentially at F_(in) and V_(low) is essentially atzero, a band range select circuit coupled to the low pass filter/drivercircuit for scaling the control signal V₂ according to the scaling valueN, wherein the low pass filter/driver circuit includes an integrator andthe oscillator drive circuit includes a range multiplier circuit havinga first input for receipt of the integrator output and a second inputfor receipt of the band range select output, said range multipliercircuit multiplying the integrator output by the value of the band rangeselect circuit output to generate control signal V₂.
 12. The system ofclaim 11 wherein the band range select circuit comprises a binary gatedswitch circuit.
 13. The system of claim 11 further comprising a pair ofvoltage level shifting current mirrors wherein the output of the rangemultiplier circuit is coupled to the oscillator drive signal source viathe current mirrors.
 14. A system having a phase-locked loop, the loopcomprisingan oscillator, a multi-input error detector circuit and anoscillator drive circuit, the loop being switchable between various onesof a plurality of preset operating frequencies wherein each one of thepreset frequencies is represented with a respective scaling value andwherein a current scaling value is represented as N, a 1/N multipliercircuit coupled to the oscillator output, the scaling value N beingapplied to the 1/N multiplier circuit, a 1/N multiple of the oscillatoroutput frequency being supplied by the 1/N multiplier circuit to theerror detector circuit as (1/N)F_(vco), the error detector circuithaving a second input for receiving an applied input signal,(1/N)F_(vco) being compared in the error detector circuit to thefrequency F_(in) of the applied input signal, the error detector circuitgenerating an output V₁ representative of phase and/or frequency errorbetween F_(in) and (1/N)F_(vco), where V₁ is equal to a fixed valueV_(ref) when there is no phase or frequency error between F_(in) and(1/N)F_(vco), the oscillator drive circuit includingan oscillator drivesignal source circuit coupled to and for supplying a drive signal to aninput of the oscillator, and a low pass filter/driver circuit forreceiving V₁ and V_(ref) and for detecting a low frequency errorcomponent V_(low) of V₁ when V₁ does not equal V_(ref), V_(low)representing the error in frequency between F_(in) and (1/N)F_(vco), thelow pass filter/driver circuit generating a control signal V₂ to aninput of the oscillator drive signal source circuit for continuouslyadjusting the drive signal according to control signal V₂ for drivingthe oscillator until (1/N)F_(vco) is essentially at F_(in) and V_(low)is essentially at zero, wherein the multi-input error detector circuitincludes a frequency comparator circuit, a phase and frequencycomparator circuit, a multiplexer circuit and a charge pump/filtercircuit, and the respective outputs of the comparators are selectivelycoupled to the charge pump/filter circuit via the multiplexer circuit.15. The system of claim 14 wherein the multiplexer circuit applies theoutput of the frequency comparator to the charge pump/filter circuitwhen the loop is switched from one to another of the plurality of presetfrequencies.
 16. A computer system having a phase-locked loopcomprising(1) a current controlled oscillator, the loop capable ofacquiring one of a plurality of preset operating frequencies for use ina system (a) which represents each of the preset frequencies with arespective value of a scaling factor, a current value of the scalingfactor being designated as N, and (b) which supplies a preset referenceclock signal at a fixed frequency F_(in) to the loop, the oscillatorcircuit having an output capable of being driven to a frequency F_(vco)which is N times the frequency of F_(in), (2) an error detector circuitfor detecting the phase difference Δ_(phase) and frequency differenceΔ_(freq) between (1/N) F_(vco) and F_(in) and for generating a controlsignal V₁ based upon Δ_(phase) and Δ_(freq), wherein control signal V₁obtains a value V_(ref) when Δ_(phase) and Δ_(freq) are at a zero level,wherein V₁ -V_(ref) is representative of Δ_(phase) and Δ_(freq), andwherein a low frequency signal component V_(low) of V₁ -V_(ref) isrepresentative of Δ_(freq), (3) a drive signal source circuit forsupplying an oscillator drive signal, (4) a frequency control circuithaving an input coupled to an output of the error detector circuit, thefrequency control circuit generating a control signal output based uponthe signal component V_(low) and coupled to an input of the drive signalsource circuit, wherein the oscillator drive signal is regulatedaccording to the value of the control signal output, (5) a scalingcircuit which scales the frequency control circuit output according tothe value N, and (6) a linearized multiplier circuit for modulating thescaled oscillator drive signal and whose output is applied as an inputto the oscillator, the linearized multiplier circuit responsive to thevalue of V₁ -V_(ref), whereby the scaled and modulated input to theoscillator serves to adjust the oscillator output to obtain the phaseand N times the frequency of F_(in).
 17. A method for controlling thefrequency and phase of an oscillator output in a phase-locked loop for amulti-band operating system wherein each band has its own band frequencyand is represented by a respective value of a scaling factor, thecurrent value of the scaling factor being designated as N, in a loopcomprising an oscillator circuit for locking onto the frequency of asystem input signal, an error detector circuit for receiving the systeminput signal, a charge pump circuit coupled to the output of the errordetector circuit, and an oscillator drive circuit having an inputcoupled to the output of the charge pump circuit and producing anoscillator drive control signal that coupled to the oscillator input fordriving the oscillator output, the oscillator output being coupled toone input of the error detector circuit and the system signal inputbeing applied to another input of the error detector circuit, the errordetector circuit issuing an error output representative of differencesin phase Δ_(phase) and frequency Δ_(freq) between the oscillator outputfrequency or a 1/N multiple thereof and the system input signalfrequency, the charge pump circuit issuing an error signal thatrepresents Δ_(freq) and Δ_(phase) based upon said error output, saidoscillator drive circuit producing said oscillator drive control signalto adjust the phase and frequency of the oscillator output, the methodcomprising the steps ofsubmitting the error signal to a filter circuitto extract a low frequency component V_(low) expressive of Δ_(freq),scaling V_(low) according to the value of N to develop a scaled V_(low)that is capable of minimizing Δ_(freq), and combining the error signalwith said scaled V_(low) to produce said oscillator drive control signalcapable of adjusting the oscillator to minimize Δ_(freq) and Δ_(phase).18. A multi-frequency operating system having a phase-locked loop forcontrolling an output frequency of an oscillator and driving said outputfrequency to a selected one of a set of frequency bands, said loopcomprisingcircuitry for detecting phase and frequency errors betweensaid oscillator output frequency and a reference frequency and producinga first error signal that represents said phase and frequency errors,said first error signal being equal to a reference level in the absenceof said phase and frequency errors, circuitry for generating a seconderror signal in response to low frequency differences between said firsterror signal and said reference level, said second error signalrepresenting an average of said frequency errors, and a controller forcombining said first error signal and said second error signal togenerate a drive signal and applying said drive signal to cause saidoscillator to adjust said output to minimize said phase and frequencyerrors, said controller including circuitry for scaling said seconderror signal in response to a change in the selected frequency bandbefore said combining to correspondingly change a relative contributionof said second error signal with respect to said first error signal insaid drive signal during changes in said selected frequency band.